LFSR Counter Generator

LFSR Counters

 

Most of the EE or CS graduates know or at least have heard about different types of hardware counters: prescaled, Johnson, ripple carry, linear feedback shift register (LFSR), and others.
The majority of logic designers use the first two types, because they’re simple to implement in Verilog or VHDL. However, for some applications LFSR counters offer a significant advantage in terms of logic utilization and maximum frequency.

The most commonly used linear function of single bits is XOR. Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value.

The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.

Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs are common.

 

Here is the VHDL Code which I used to make a 8-Bit Linear Feedback Shift Register,

 

——————————————————————————-
— Copyright (C) 2009 OutputLogic.com
— This source file may be used and distributed without restriction
— provided that this copyright statement is not removed from the file
— and that any derivative work contains the original copyright notice
— and the associated disclaimer.

— THIS SOURCE FILE IS PROVIDED “AS IS” AND WITHOUT ANY EXPRESS
— OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
— WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
——————————————————————————-
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lfsr is
port (
ctrl , rst, clk : in std_logic;
op : out std_logic);
end lfsr;

architecture my_lfsr of lfsr is
signal lfsr: std_logic_vector (3 downto 0);
signal d0ne, lfsr_eq: std_logic;
begin

d0ne <= lfsr(3) xnor lfsr(2) ;

process(lfsr) begin
if(lfsr = x”6″) then
lfsr_eq <= ‘1’;
else
lfsr_eq <= ‘0’;
end if;
end process;

process (clk,rst) begin
if (rst = ‘1’) then
lfsr <= “0000”;
op <= ‘0’;
elsif (clk’EVENT and clk = ‘1’) then
op <= lfsr_eq;
if (ctrl = ‘1’) then
if(lfsr_eq = ‘1’) then
lfsr <= “0000”;
else
lfsr <= lfsr(2 downto 0) & d0ne;
end if;
end if;
end if;
end process;
end architecture my_lfsr;

 

For Further Help and Assistance,Refer to:8-bit LFSR Counter Generator.

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